In the manufacturing process of a known sensor, for instance an absolute pressure sensor, cf. FIGS. 1 and 2, two semiconductor wafers or simply wafers are joined to each other in a laminar manner by bonding. This is achieved such that recesses (cavities) formed in the front side of the first semiconductor wafer as the cavities of a cavity wafer are covered and hermetically sealed under vacuum conditions by means of the second semiconductor wafer acting as a cover wafer. By means of grinding, polishing or etching of the stack formed by the bonding process the bonded cover wafer is thinned into a membrane of defined thickness. In this state, at least one electronic structure has to be implemented into the it) semiconductor wafer surface of the membrane obtained by the thinning process in order to evaluate pressure dependent deformations of the membrane; the membrane's orientation has to be in defined relationship to the geometry of the cavities that are no longer visible.
To this end, according to well-established techniques rear side alignment marks (on the wafer) are provided on the rear side of the cavity wafer in a first step of the process flow, which alignment marks are then used to align the mask for the cavities by alignment of the front side to the rear side (as “front to back side alignment”) by means of alignment marks on the mask. In this way, front side alignment marks are obtained on the wafer, which are aligned to the wafer alignment marks on the rear side. During the bonding process of the cover wafer the front side alignment marks are covered. After the bonding and thinning processes the CMOS structure has to be positioned by means of the rear side alignment marks on the wafer via the masks defining the CMOS structure. Only then the CMOS structure is in a defined position with respect to the structure comprised of several cavities that is no longer visible.
This method is disadvantageous in that the cavity wafer has to be manipulated at its front side (in the sense of handled) for the generation of the rear side marks so that damage, for instance imprints of a chuck or scratches may occur. Also, the achievable precision is lowered due to the necessity of a double alignment of front side to rear side (a respective mask to the rear side marks).
According to DE 42 23 455 A1 (Mitsubishi Denki) a semiconductor pressure sensor (sensor) comprises a first silicon substrate and a second silicon substrate with a primary surface on which is formed a device having diffused resistors and a diffused wiring system. A secondary surface that is bonded or joined to a primary surface of the first silicon substrate comprises an intermediate insulation layer between the primary surface of the first silicon substrate and the secondary surface of the second silicon substrate, wherein the intermediate insulation layer includes a section that forms a vacuum chamber and there are sections provided which form alignment marks. Alignment is mark observation windows are formed on those sections of the second silicon substrate that correspond to the respective sections of the alignment marks, and a silicon oxide layer formed on the primary surface of the second silicon substrate is provided so as to protect the device and the alignment mark observation windows. This sensor comprises indentations or recesses in the shape of holes that are not positioned at the edge so that they have to correspond to the alignment marks of the lower wafer in a spatially precise manner. Openings in the vicinity of the useable wafer surface are associated with pronounced structuring issues, in particular an inhomogeneous stress load, the creation of “resist residues” and turbulences during rotating wet chemical processes.
According to DE 10 2004 006 494 A1 (Mitsubishi Denki) there is provided a semiconductor wafer having a front side surface that is a flat surface with a semiconductor circuit formed thereon and to which a carrier plate is attached. The rear side surface is partially removed in order to reduce the thickness thereof. A separation section is formed at an edge section of the semiconductor wafer, which separation section comprises a cavity that is deeper than the final thickness of the semiconductor wafer obtained partially by removing the rear side surface. The separation section has a length that extends from the flat surface gradually outwardly and that is greater than a total sum of the difference between the maximum and the minimum of the final tolerances of the diameter of the semiconductor wafer and of the carrier plate, which substantially has the same diameter as the semiconductor wafer. A maximum value of an alignment error is created between the semiconductor wafer and the carrier plate, wherein the alignment error is caused at the time of joining the components to each other. In this manner, a semiconductor wafer is to be provided in which a transport system for the semiconductor wafer may commonly be used prior to and after a carrier plate is attached to the semiconductor wafer and for which the final precision of the semiconductor wafer and the positioning or handling accuracy of the semiconductor wafer and the carrier plate are less critical. In this manner, enhanced efficiency during the fabrication of semiconductor devices is achieved.
US 2005/0013019 A1 (Tseng et al) discloses a method for photolithographic precision alignment of a wafer after bonding, wherein two cavities are formed on the rear side surface of the upper wafer at positions—corresponding to the alignment marks on the lower wafer. The depth of both cavities is deeper than that of the membrane structure. The upper wafer is then bonded to the lower wafer which already includes alignment marks and a microstructure. Thereafter, a thinning process is performed until the thickness of the upper wafer is less than the depth of the cavities so that the alignment marks may be joined with the cavities and may thus act as alignment marks for the exposure. Thus, structures are formed in the cover wafer and are opened by the thinning process and have to correspond to the alignment marks of the buried layer. Due to this fact the same difficulties are encountered in this case as in the above-identified DE 4223455 A1.
DE 19913612 C1 (Fraunhofer Society) relates to the fabrication of alignment structures for the photolithography processes in silicon wafers. The method for generating alignment structures in semiconductor substrates during the fabrication of devices includes the steps: providing a first substrate, on which is formed a first layer; patterning the first layer in order to form first portions that are necessary for the functioning of the devices; bonding the first substrate to a second substrate such that the first layer is positioned between the two substrates; thinning the first and second substrates down to a residual thickness. In this manner, the alignment structures are formed prior to bonding the first substrates to the second substrates in the form of portions which extend completely through the first layer—however not through the possibly thinned first substrate—and have an index of refraction that is different from the index of refraction of adjacent portions. The structures are based on local changes of the index of refraction or the damping within or below a thin silicon layer such that the topography of the wafer surface is not changed or affected. The alignment structures are visible for an exposure device in the red or infrared light range and in particular by using a dark field exposure.